ESP Chip Errata Choose target... Choose version... ESP32-S2 Series SoC Errata Chip Revision Identification Errata Summary All Errata Descriptions Errata Descriptions by Chip Revisions Revision History Resources and Legal Notices Related Documentation and Resources Disclaimer and Copyright Notice ESP Chip Errata ESP32-S2 Series SoC Errata Download PDF ESP32-S2 Series SoC Errata [中文] This document describes known errata in ESP32-S2 series of SoCs. It consists of the following major chapters: Chip Revision Identification Introduces how to identify a specific ESP32-S2 chip revision, or a batch of chips and products built around the ESP32-S2 chips which contains error fixes described in this document. Errata Summary Overview of all bugs and their affected chip revisions. All Errata Descriptions Detailed bug descriptions, including conditions, expected behaviors and actual behaviors, causes, influences on users, workarounds, and solutions. Errata Descriptions by Chip Revisions Classification of bug descriptions by chip revisions. Revision History The release notes for this document. To switch to another chip, use the drop-down menu at the top left of the page. Next Suggestion on this document? Provide feedback Help improve this document? Edit on GitHub Need more information? Check ESP forum Sales Questions Technical Inquiries © Copyright 2024 - 2026, Espressif Systems (Shanghai) Co., Ltd Built with Sphinx using a theme based on Read the Docs Sphinx Theme. ESP Chip Errata Choose target... Choose version... ESP32-S2 Series SoC Errata Chip Revision Identification Errata Summary All Errata Descriptions Errata Descriptions by Chip Revisions v0.0 (9) [I2C-97] The Falling Edge of RTC_I2C_RESET Triggers Reset at Low Temperature [ADC-112] Bit 1 of SAR ADC Does Not Flip [SPI-106] SPI Is Stuck After Soft Restart from Auto Suspension [SYSTEM-86] Leakage Current at the VDDA and VDD3P3_RTC Pins during Shutdown [SYSTEM-117] Random Flash Download Failure Description Workarounds Solution [TOUCH-99] The Scan Done Interrupt RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA Occurs Twice During a Single Scan [USB-105] Abnormal Data During AHB Bus Arbitration by USB OTG [RTC-126] RTC Register Read Error After Wake-up from Light-sleep Mode [TOUCH-100] The TOUCH_SCAN_DONE_INT Interrupt Raw Data Value Is Undefined v1.0 (3) Revision History Resources and Legal Notices Related Documentation and Resources Disclaimer and Copyright Notice ESP Chip Errata Errata Descriptions by Chip Revisions Chip Revision: v0.0 [SYSTEM-117] Random Flash Download Failure Download PDF [SYSTEM-117] Random Flash Download Failure Affected revisions: v0.0 Description In download mode, the first stage bootloader in ROM receives serial data from two different input pins. Among the two input pins, pin 24 DAC_2 (GPIO18) is not pulled up by default. If this pin is not pulled up in PCB design and is left floating, in download mode the first stage bootloader will not function properly (including download applications) due to interference. Workarounds This problem can be bypassed in PCB design by pulling up pin 24 DAC_2. The typical value of the pull-up resistor is 10 kΩ. All official development boards by Espressif pull this pin up, while official modules are not. Solution Fixed in chip revision v1.0 by pulling pin 24 up by default. Next Previous Suggestion on this document? Provide feedback Help improve this document? Edit on GitHub Need more information? Check ESP forum Sales Questions Technical Inquiries © Copyright 2024 - 2026, Espressif Systems (Shanghai) Co., Ltd Built with Sphinx using a theme based on Read the Docs Sphinx Theme. ESP Chip Errata Choose target... Choose version... ESP32-S2 Series SoC Errata Chip Revision Identification Errata Summary All Errata Descriptions Errata Descriptions by Chip Revisions v0.0 (9) v1.0 (3) [TOUCH-99] The Scan Done Interrupt RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA Occurs Twice During a Single Scan [RTC-126] RTC Register Read Error After Wake-up from Light-sleep Mode Description Workarounds Solution [TOUCH-100] The TOUCH_SCAN_DONE_INT Interrupt Raw Data Value Is Undefined Revision History Resources and Legal Notices Related Documentation and Resources Disclaimer and Copyright Notice ESP Chip Errata Errata Descriptions by Chip Revisions Chip Revision: v0.0 [RTC-126] RTC Register Read Error After Wake-up from Light-sleep Mode Download PDF [RTC-126] RTC Register Read Error After Wake-up from Light-sleep Mode Affected revisions: v0.0 v1.0 Description If an RTC peripheral is turned off in Light-sleep mode, there is a certain probability that after waking up from Light-sleep, the CPU of ESP32-S2 will read the registers in the RTC power domain incorrectly. Workarounds Users are suggested not to power down RTC peripherals in Light-sleep mode. There will be no impact on power consumption. Solution No fix scheduled. Next Previous Suggestion on this document? Provide feedback Help improve this document? Edit on GitHub Need more information? Check ESP forum Sales Questions Technical Inquiries © Copyright 2024 - 2026, Espressif Systems (Shanghai) Co., Ltd Built with Sphinx using a theme based on Read the Docs Sphinx Theme. ESP Chip Errata Choose target... Choose version... ESP32-S2 Series SoC Errata Chip Revision Identification Errata Summary All Errata Descriptions Errata Descriptions by Chip Revisions v0.0 (9) [I2C-97] The Falling Edge of RTC_I2C_RESET Triggers Reset at Low Temperature [ADC-112] Bit 1 of SAR ADC Does Not Flip [SPI-106] SPI Is Stuck After Soft Restart from Auto Suspension [SYSTEM-86] Leakage Current at the VDDA and VDD3P3_RTC Pins during Shutdown Description Workarounds Solution [SYSTEM-117] Random Flash Download Failure [TOUCH-99] The Scan Done Interrupt RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA Occurs Twice During a Single Scan [USB-105] Abnormal Data During AHB Bus Arbitration by USB OTG [RTC-126] RTC Register Read Error After Wake-up from Light-sleep Mode [TOUCH-100] The TOUCH_SCAN_DONE_INT Interrupt Raw Data Value Is Undefined v1.0 (3) Revision History Resources and Legal Notices Related Documentation and Resources Disclaimer and Copyright Notice ESP Chip Errata Errata Descriptions by Chip Revisions Chip Revision: v0.0 [SYSTEM-86] Leakage Current at the VDDA and VDD3P3_RTC Pins during Shutdown Download PDF [SYSTEM-86] Leakage Current at the VDDA and VDD3P3_RTC Pins during Shutdown Affected revisions: v0.0 Description When a chip is connected to the power supply, but the CHIP_PU pin is held low (meaning that the chip powers off), there will be a leakage current in the µA range at power pins such as VDDA and VDD3P3_RTC. Workarounds None. Solution Fixed in chip revision v1.0. Next Previous Suggestion on this document? Provide feedback Help improve this document? Edit on GitHub Need more information? Check ESP forum Sales Questions Technical Inquiries © Copyright 2024 - 2026, Espressif Systems (Shanghai) Co., Ltd Built with Sphinx using a theme based on Read the Docs Sphinx Theme. ESP Chip Errata Choose target... Choose version... ESP32-S2 Series SoC Errata Chip Revision Identification Chip Revision Numbering Scheme Primary Identification Methods eFuse Bits Chip Marking Module Marking Additional Identification Methods Date Code PW Number ESP-IDF Release Compatibility Related Documents Errata Summary All Errata Descriptions Errata Descriptions by Chip Revisions Revision History Resources and Legal Notices Related Documentation and Resources Disclaimer and Copyright Notice ESP Chip Errata Chip Revision Identification Download PDF Chip Revision Identification [中文] Espressif is introducing a new vM.X numbering scheme to indicate chip revisions. This guide outlines the structure of this scheme and provides information on chip errata and additional identification methods. Chip Revision Numbering Scheme The new numbering scheme vM.X consists of the major and minor numbers described below. M – Major number, indicating the major revision of the chip product. If this number changes, it means the software used for the previous version of the product is incompatible with the new product, and the software version shall be upgraded for the use of the new product. X – Minor number, indicating the minor revision of the chip product. If this number changes, it means the software used for the previous version of the product is compatible with the new product, and there is no need to upgrade the software. The vM.X scheme replaces previously used chip revision schemes, including ECOx numbers, Vxxx, and other formats if any. Primary Identification Methods eFuse Bits The chip revision is encoded using two eFuse fields: EFUSE_RD_MAC_SPI_SYS_3_REG[20:18] EFUSE_RD_MAC_SPI_SYS_4_REG[6:4] Table 1 Chip Revision Identification by eFuse Bits eFuse Bit Chip Revision v0.0 v1.0 Major Number EFUSE_RD_MAC_SPI_SYS_3_REG[19] 0 0 EFUSE_RD_MAC_SPI_SYS_3_REG[18] 0 1 Minor Number EFUSE_RD_MAC_SPI_SYS_3_REG[20] 0 0 EFUSE_RD_MAC_SPI_SYS_4_REG[6] 0 0 EFUSE_RD_MAC_SPI_SYS_4_REG[5] 0 0 EFUSE_RD_MAC_SPI_SYS_4_REG[4] 0 0 Chip Marking Espressif Tracking Information line in chip marking Figure 1 Chip Marking Diagram Table 2 Chip Revision Identification by Chip Marking Chip Revision Espressif Tracking Information v0.0 X A XXXXXXXX v1.0 X B XXXXXXXX Module Marking Specification Identifier line in module marking Figure 2 Module Marking Diagram Table 3 Chip Revision Identification by Module Marking Chip Revision Specification Identifier v0.0 XX XXXX v1.0 MB XXXX Additional Identification Methods Date Code Some errors in the chip product don’t need to be fixed at the silicon level, or in other words in a new chip revision. In this case, the chip may be identified by Date Code in chip marking (see Chip Marking). For more information, please refer to ESP32-S2 Chip Packaging Information > Chip Silk Marking. PW Number Modules built around the chip may be identified by PW Number in product label (see Module Product Label). For more information, please refer to ESP32-S2 Module Packaging Information > Pizz